The present invention relates to programmable CMOS devices, and more specifically, programmable CMOS devices comprising an NFET and a PFET with a commonly connected floating gate for storing electrical charges and methods of operating the same.
A field effect transistor (FET) typically includes a source region and a drain region, with a channel region in between. The conductance of the channel region is controlled by the voltage on a conductive gate electrode which is separated from the channel region by an insulator layer, which is typically referred to as a gate dielectric. For an n-type FET (NFET), the source and drain regions are heavily doped with n-type dopants. For a p-type FET (PFET), the source and drain regions are doped with p-type dopants.
For an NFET, the channel conductance can be increased, that is the electron current flowing from source to drain can be increased, by biasing the gate electrode more positively relatively to its source region. Conversely, the channel conductance can be decreased, that is the electron current flowing from source to drain can be decreased, by biasing the gate electrode more negatively relatively to its source region. For a PFET, the channel conductance can be increased, that is, the hole current flowing from source to drain can be increased, by biasing the gate electrode more negatively relatively to its source region. The channel conductance can be decreased, that is, the hole current flowing from source to drain can be decreased, by biasing the gate electrode more positively relatively to its source region. The charge carrier flow between the source and the drain is referred to as the drain current.
For a typical FET, the gate current, i.e., the current flow between the gate electrode and the source, drain, or channel region, is orders of magnitude less than the current between the source and the drain. The gate current is controlled by tunneling processes. If the gate insulator is of sufficient thickness, tunneling is negligible and no current flows between the gate electrode and the source, drain, or channel region. In contrast, the gate current increases in a FET having a thin gate dielectric.
Referring to FIG. 1, the gate current and the drain current are shown as a function of a gate voltage, i.e., the voltage applied between the gate electrode and the source, at a fixed drain-to-source bias voltage of 6 V for a PFET having a 7 nm-thick gate oxide and a gate length of 0.65 μm. The gate current is caused by tunneling of avalanche hot electrons into the gate electrode.
Referring to FIG. 2, a schematic curve for the gate current illustrates that the dominant charge carriers contributing to the gate current of a PFET having a constant drain-to-source voltage are avalanche hot electrons in a low gate-to-source voltage mode, but are channel hot holes in a high gate-to-source voltage mode. The gate-to-source voltage at which a transition between the two modes occurs depends on the characteristics of the PFET.
Referring to FIG. 3, a schematic curve for the gate current illustrates that the dominant charge carriers contributing to the gate current of an NFET having a constant drain-to-source voltage are avalanche hot holes in a low gate-to-source voltage mode, but are channel hot electrons in a high gate-to-source voltage mode. The gate-to-source voltage at which a transition between the two modes occurs depends on the characteristics of the NFET.
The concept of flash memory was first described in F. Masuoka et al., “A new flash EEPROM cell using triple polysilicon technology,” IEEE IEDM Technical Digest, p. 464, 1984. Today, most non-volatile memory products are flash memory. While such floating-gate devices can be programmed by injecting charge into the floating gate, these floating-gate programmable devices have specialized applications that require specific manufacturing processes. Typically, stand-alone non-volatile memory chips are designed with high memory capacity and low cost as primary objectives. These chips are made using special processes that are not compatible with standard logic processes. For instance, the first flash memory described by Masuoka et al. in 1984, mentioned above, employs three layers of polysilicon, while standard logic processes employ only one layer of polysilicon. In short, prior art floating gate memory devices require additional layers, and correspondingly, additional processing steps during the manufacturing process.